| 1 |
Palchaudhuri A., Dhar A. S., Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies, Journal of Parallel and Distributed Computing, 130, 110-125, 2019 |
| 2 |
Mula S., Gogineni V. C., Dhar A. S., Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1223-1227, 2019 |
| 3 |
Kulshreshtha T., Dhar A. S., CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation, Circuits, Systems, and Signal Processing, 37, 5101-5126, 2018 |
| 4 |
Mukherjee A., Dhar A. S., Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method, Circuits, Systems, and Signal Processing, 37, 5595-5615, 2018 |
| 5 |
Kulshreshtha T., Dhar A. S., CORDIC-based Hann windowed sliding DFT architecture for real-time spectrum analysis with bounded error-accumulation, IET Circuits, Devices & Systems, 11, 487-495, 2017 |
| 6 |
Palchaudhuri A., Amresh A. A., Dhar A. S., Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs, Journal of Cellular Automata, 12, 217-247, 2017 |
| 7 |
Ghosh A., Dhar A. S., Halder A., Fraction phase based low energy frequency calibration: analysis and design, IET Circuits, Devices & Systems, 241-249, 2017 |
| 8 |
Mukherjee R., Mahajan V. , Dhar A. S., Chakrabarti I., High Performance VLSI Design of Diamond Search Algorithm for Fast Motion Estimation, Journal of Circuits, Systems and Computers, 25, 16501141-165011416, 2016 |
| 9 |
Panigrahy M., Chakrabarti I. , Dhar A. S., Low-Delay Parallel Architecture for Fractal Image Compression, Circuits, Systems, and Signal Processing, 35, 897-917, 2016 |
| 10 |
Mukherjee A., Dhar A. S., Real-time fault-tolerance with hot-standby topology for conditional sum adder, Microelectronics Reliability, 55, 704-712, 2015 |
