| 1 |
Mukherjee P., Jain K. , Chattopadhyay S, Thermal-Aware Task Allocation and Scheduling fpr Periodic Real-Time Applications in Mesh based Heterogeneous NoCs, Real-Time Systems, 1-36, 2019 |
| 2 |
Manna K., Sagar C. , Chattopadhyay S. , Sengupta I., Thermal-aware test scheduling strategy for network-on-chip based systems, ACM Journal on Emerging Technologies in Computing (JETC), 15, 2019 |
| 3 |
Prasad N., Chattopadhyay S. , Chakrabarti I, An Energy Efficient Network-on-Chip based Reconfigurable Viterbi Decoder Architecture, IEEE Transactions on Circuits and Systems I, 65, 3543-3554, 2018 |
| 4 |
Chattopadhyay S., Area conscious state assignment with flip-flop and output polarity selection for finite state machine synthesis - a genetic algorithm approach, The Computer Journal, 48, 443-450, 2005 |
| 5 |
Chattopadhyay S., Reddy P. N, Finite state machine state assignment targeting low power consumption, IEE Proceedings-Computers and Digital Techniques, 151, 61-70, 2004 |
| 6 |
Dasgupta P., Chattopadhyay S. , Chaudhuri P. P., Sengupta I., Cellular automata-based recursive pseudoexhaustive test pattern generator, IEEE Transactions on Computers, 50, 177-185, 2001 |
| 7 |
Chattopadhyay S, Low power state assignment and flipflop selection for finite state machine synthesis - a genetic algorithmic approach, IEE Proceedings-Computers and Digital Techniques, 148, 2001 |
| 8 |
Dasgupta P., Chattopadhyay S. , Sengupta I., Theory and application of non-group cellular automata for message authentication, Journal of Systems Architecture, 47, 383-404, 2001 |
| 9 |
Chattopadhyay S., Sengupta S. , Adhikari S. , Pal M., Highly regular, modular, and cascadable design of cellular automata-based pattern classifier, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8, 724-735, 2000 |
| 10 |
Chattopadhyay S., Chowdhury D. R., Bhattacharjee S. , Chaudhuri P. P., Cellular-automata-array-based diagnosis of board level faults, IEEE transactions on computers, 47, 817-828, 1998 |
| 11 |
Chattopadhyay S., Roy S. , Chaudhuri P. P., KGPMIN: An efficient multilevel multioutput AND-OR-XOR minimizer, IEEE transactions on computer-aided design of integrated circuits and systems, 1997 |
| 12 |
Sasidhar K., Chattopadhyay S. , Chaudhuri P. P., CAA decoder for cellular automata based byte error correcting code, IEEE transactions on computers, 45, 1003-1016, 1996 |
| 13 |
Chattopadhyay S., Roy S. , Chaudhuri P. P., Synthesis of highly testable fixed-polarity AND-XOR canonical networks-A genetic algorithm-based approach, IEEE transactions on computers, 45, 487-490, 1996 |
| 14 |
Chattopadhyay S., Roy S. , Chaudhuri P. P., KGPMAP: library-based technology-mapping technique for antifuse based FPGAs, IEE Proceedings-Computers and Digital Techniques, 141, 361-368, 1994 |
