| 1 |
N. P., Chattopadhyay S. , Chakrabarti I., Energy-Efficient and Secure Network-on-Chip Architectures for DSP Applications, 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID, 1-6, 2019 |
| 2 |
Karmakar R., Prasad N. , Chattopadhyay S. , Kapur R. , Sengupta I., A New Logic Encryption Strategy Ensuring Key Interdependency, VLSI Design, 429-434, 2017 |
| 3 |
Prasad N., Karmakar R. , Chattopadhyay S. , Chakrabarti I., Runtime mitigation of illegal packet request attacks in Networks-on-Chip, ISCAS, 1-4, 2017 |
| 4 |
Chatterjee N., Mukherjee P. , Chattopadhyay S, A strategy for fault tolerant reconfigurable Network-on-Chip design, VDAT, 1-2, 2016 |
| 5 |
Manna K., Chattopadhyay S. , Sengupta I., Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip, ISVLSI, 583-586, 2016 |
| 6 |
Manna K., Sagar C. S., Chattopadhyay S. , Sengupta I., Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs, ISVLSI, 529-534, 2016 |
| 7 |
Nuthakki S. S., Karmakar R. , Chattopadhyay S. , Chakrabarty K., Optimization of the IEEE 1687 access network for hybrid access schedules, VTS, 1-6, 2016 |
| 8 |
Karmakar R., Chattopadhyay S., Thermal-Safe Schedule Generation for System-on-Chip Testing, VLSI Design, 475-480, 2016 |
| 9 |
De'souza S., Soumya J. , Chattopadhyay S., A constructive heuristic for application mapping onto an express channel based Network-on-Chip, VDAT, 1-6, 2015 |
| 10 |
Dutta A., Kundu S. , Chattopadhyay S. , Das B. K., A hardware based low temperature solution for VLSI testing using decompressor side masking, Dutta A., Kundu S. , Chattopadhyay S. , Das B. K., 637-640, 2015 |
| 11 |
Nuthakki S. S., Chattopadhyay S., An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets, ATS, 151-156, 2015 |
| 12 |
Chatterjee N., Chattopadhyay S., Fault tolerant mesh based Network-on-Chip architecture, ISCAS, 417-420, 2015 |
| 13 |
Bhar A., Chattopadhyay S. , Sengupta I. , Kapur R., GA based diagnostic test pattern generation for transition faults, VDAT, 1-6, 2015 |
| 14 |
Dutta A., Chattopadhyay S., Particle swarm optimization approach for low temperature BIST, VDAT, 1-6, 2015 |
| 15 |
Chattopadhyay S, Power- and thermal-aware testing of VLSI circuits and systems, VDAT, 1-1, 2015 |
| 16 |
Karmakar R., Agarwal A. , Chattopadhyay S., Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints, ATS, 73-78, 2015 |
| 17 |
Karmakar R., Agarwal A. , Chattopadhyay S, Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach, VTS, 1-6, 2015 |
| 18 |
Nuthakki S. S., Chattopadhyay S. , Chakraborty M., Test set customization for improved fault diagnosis without sacrificing coverage, ISCAS, 1574-1577, 2015 |
| 19 |
Karmakar R., Chattopadhyay S., Thermal-Aware Test Data Compression Using Dictionary Based Coding, VLSI Design, 53-58, 2015 |
| 20 |
Manna K., Teja V. S., Chattopadhyay S. , Sengupta I., TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning, ISVLSI, 392-397, 2015 |
