The research interest of my group spans over Network-on-Chip Design and Test, Power- and Thermal-Aware Testing of Digital Circuits and Systems, Logic Encryption and Design for Security. Network-on-Chip (NoC) is an embedded System-on-Chip (SoC) design paradigm. In this, functional modules within a chip communicate between themselves using an on-chip router network. Routers with very simple architecture are interconnected either in some regular (such as mesh, tree topologies) or in a customized fashion. Electrical signal exchanges are replaced by message passing through the network, resolving the issue of bandwidth limitation of the bus. This leads to the problems of router architecture design, topology design, power minimization, mapping an application onto such a topology, reconfiguration, ensuring timeliness of tasks, etc. Our research works to address all these issues. Power and thermal aware test techniques are important for digital systems due to the limited battery life, high power consumption, and heat generation during a test. Compared to the normal mode of operation, in test mode, power consumption can go up by three times, increasing heat dissipation and the creation of thermal hot-spots. Test algorithms and techniques have been developed to address these issues. Both circuit- and system-level solutions have been proposed. Design for Security (DfS) attempts to protect the IP of a design manufactured at the third-party foundry. Protection is sought to prevent IP piracy, overproduction, etc. Logic encryption incorporates some key gates into the design. The keys are not available to the manufacturer. Once it comes back to the designer, the keys are provided in tamper-proof memory, thus protecting the IP. Extensive research is being carried out in our group to develop efficient techniques for logic encryption. Finally, we are also working on developing machine learning algorithms to solve EDA problems in VLSI design and test. A number of works in this direction have been initiated ranging from NoC application mapping to low power test.
