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Santanu Chattopadhyay


Research Statement

The research interest of my group spans over Network-on-Chip Design and Test, Power- and Thermal-Aware Testing of Digital Circuits and Systems, Logic Encryption and Design for Security. Network-on-Chip (NoC) is an embedded System-on-Chip (SoC) design paradigm. In this, functional modules within a chip communicate between themselves using an on-chip router network. Routers with very simple architecture are interconnected either in some regular (such as mesh, tree topologies) or in a customized fashion. Electrical signal exchanges are replaced by message passing through the network, resolving the issue of bandwidth limitation of the bus. This leads to the problems of router architecture design, topology design, power minimization, mapping an application onto such a topology, reconfiguration, ensuring timeliness of tasks, etc. Our research works to address all these issues. Power and thermal aware test techniques are important for digital systems due to the limited battery life, high power consumption, and heat generation during a test. Compared to the normal mode of operation, in test mode, power consumption can go up by three times, increasing heat dissipation and the creation of thermal hot-spots. Test algorithms and techniques have been developed to address these issues. Both circuit- and system-level solutions have been proposed. Design for Security (DfS) attempts to protect the IP of a design manufactured at the third-party foundry. Protection is sought to prevent IP piracy, overproduction, etc. Logic encryption incorporates some key gates into the design. The keys are not available to the manufacturer. Once it comes back to the designer, the keys are provided in tamper-proof memory, thus protecting the IP. Extensive research is being carried out in our group to develop efficient techniques for logic encryption. Finally, we are also working on developing machine learning algorithms to solve EDA problems in VLSI design and test. A number of works in this direction have been initiated ranging from NoC application mapping to low power test.


  • 1 VLSI And Embedded Systems
  • 2 Network-on-Chip Design And Test
  • 3 Low Power Digital Design And Testing
  • 4 Thermal Aware Testing
  • 5 Logic Encryption


  • N. P., Chattopadhyay S. , Chakrabarti I., Energy-Efficient and Secure Network-on-Chip Architectures for DSP Applications, 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID, 1-6, 2019
  • Mukherjee P., Jain K. , Chattopadhyay S, Thermal-Aware Task Allocation and Scheduling fpr Periodic Real-Time Applications in Mesh based Heterogeneous NoCs, Real-Time Systems, 1-36, 2019
  • Manna K., Sagar C. , Chattopadhyay S. , Sengupta I., Thermal-aware test scheduling strategy for network-on-chip based systems, ACM Journal on Emerging Technologies in Computing (JETC), 15, 2019
  • Prasad N., Chattopadhyay S. , Chakrabarti I, An Energy Efficient Network-on-Chip based Reconfigurable Viterbi Decoder Architecture, IEEE Transactions on Circuits and Systems I, 65, 3543-3554, 2018
  • Karmakar R., Prasad N. , Chattopadhyay S. , Kapur R. , Sengupta I., A New Logic Encryption Strategy Ensuring Key Interdependency, VLSI Design, 429-434, 2017
  • Prasad N., Karmakar R. , Chattopadhyay S. , Chakrabarti I., Runtime mitigation of illegal packet request attacks in Networks-on-Chip, ISCAS, 1-4, 2017
  • Chatterjee N., Mukherjee P. , Chattopadhyay S, A strategy for fault tolerant reconfigurable Network-on-Chip design, VDAT, 1-2, 2016
  • Manna K., Chattopadhyay S. , Sengupta I., Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip, ISVLSI, 583-586, 2016
  • Manna K., Sagar C. S., Chattopadhyay S. , Sengupta I., Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs, ISVLSI, 529-534, 2016
  • Nuthakki S. S., Karmakar R. , Chattopadhyay S. , Chakrabarty K., Optimization of the IEEE 1687 access network for hybrid access schedules, VTS, 1-6, 2016
  • Karmakar R., Chattopadhyay S., Thermal-Safe Schedule Generation for System-on-Chip Testing, VLSI Design, 475-480, 2016
  • De'souza S., Soumya J. , Chattopadhyay S., A constructive heuristic for application mapping onto an express channel based Network-on-Chip, VDAT, 1-6, 2015
  • Dutta A., Kundu S. , Chattopadhyay S. , Das B. K., A hardware based low temperature solution for VLSI testing using decompressor side masking, Dutta A., Kundu S. , Chattopadhyay S. , Das B. K., 637-640, 2015
  • Nuthakki S. S., Chattopadhyay S., An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets, ATS, 151-156, 2015
  • Chatterjee N., Chattopadhyay S., Fault tolerant mesh based Network-on-Chip architecture, ISCAS, 417-420, 2015
  • Bhar A., Chattopadhyay S. , Sengupta I. , Kapur R., GA based diagnostic test pattern generation for transition faults, VDAT, 1-6, 2015
  • Dutta A., Chattopadhyay S., Particle swarm optimization approach for low temperature BIST, VDAT, 1-6, 2015
  • Chattopadhyay S, Power- and thermal-aware testing of VLSI circuits and systems, VDAT, 1-1, 2015
  • Karmakar R., Agarwal A. , Chattopadhyay S., Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints, ATS, 73-78, 2015
  • Karmakar R., Agarwal A. , Chattopadhyay S, Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach, VTS, 1-6, 2015
  • Nuthakki S. S., Chattopadhyay S. , Chakraborty M., Test set customization for improved fault diagnosis without sacrificing coverage, ISCAS, 1574-1577, 2015
  • Karmakar R., Chattopadhyay S., Thermal-Aware Test Data Compression Using Dictionary Based Coding, VLSI Design, 53-58, 2015
  • Manna K., Teja V. S., Chattopadhyay S. , Sengupta I., TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning, ISVLSI, 392-397, 2015
  • Chattopadhyay S., Area conscious state assignment with flip-flop and output polarity selection for finite state machine synthesis - a genetic algorithm approach, The Computer Journal, 48, 443-450, 2005
  • Chattopadhyay S., Reddy P. N, Finite state machine state assignment targeting low power consumption, IEE Proceedings-Computers and Digital Techniques, 151, 61-70, 2004
  • Dasgupta P., Chattopadhyay S. , Chaudhuri P. P., Sengupta I., Cellular automata-based recursive pseudoexhaustive test pattern generator, IEEE Transactions on Computers, 50, 177-185, 2001
  • Chattopadhyay S, Low power state assignment and flipflop selection for finite state machine synthesis - a genetic algorithmic approach, IEE Proceedings-Computers and Digital Techniques, 148, 2001
  • Dasgupta P., Chattopadhyay S. , Sengupta I., Theory and application of non-group cellular automata for message authentication, Journal of Systems Architecture, 47, 383-404, 2001
  • Chattopadhyay S., Sengupta S. , Adhikari S. , Pal M., Highly regular, modular, and cascadable design of cellular automata-based pattern classifier, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8, 724-735, 2000
  • Chattopadhyay S., Chowdhury D. R., Bhattacharjee S. , Chaudhuri P. P., Cellular-automata-array-based diagnosis of board level faults, IEEE transactions on computers, 47, 817-828, 1998
  • Chattopadhyay S., Roy S. , Chaudhuri P. P., KGPMIN: An efficient multilevel multioutput AND-OR-XOR minimizer, IEEE transactions on computer-aided design of integrated circuits and systems, 1997
  • Sasidhar K., Chattopadhyay S. , Chaudhuri P. P., CAA decoder for cellular automata based byte error correcting code, IEEE transactions on computers, 45, 1003-1016, 1996
  • Chattopadhyay S., Roy S. , Chaudhuri P. P., Synthesis of highly testable fixed-polarity AND-XOR canonical networks-A genetic algorithm-based approach, IEEE transactions on computers, 45, 487-490, 1996
  • Chattopadhyay S., Roy S. , Chaudhuri P. P., KGPMAP: library-based technology-mapping technique for antifuse based FPGAs, IEE Proceedings-Computers and Digital Techniques, 141, 361-368, 1994


  • Synopsys CAD Laboratory Project Phase II, Client: Synopsys Inc., Co-P.I.: Santanu Chattopadhyay, Completed
  • Developing Design-for-Security Techniques in Integrated Circuits via Logic Encryption, Client: Department of Science and Technology (DST), Govt. of West Bengal, P.I.: Santanu Chattopadhyay, Completed
  • Machine Learning Approaches for Test and Diagnosis of Digital VLSI Circuits, Client: Synopsys Inc., P.I.: Santanu Chattopadhyay, Completed

Research Group

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Ajay Khare
Ph. D.
Research Scholars
Embedded Systems
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Kaushik Khatua
Ph. D.
Research Scholars
Machine learning techniques for VLSI design
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Rajit Karmakar
Ph. D.
Research Scholars
VLSI testing
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Sambangi Ramesh
Ph. D.
Research Scholars
Machine learning architerure design