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Pradip Mandal


  • Associate Professor at the Dept. of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur since 27th May 2011
  • Assistant Professor at the Dept. of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur From 24th May 2004 to 26th May 2011
  • Teaching/taught Analog Electronic Circuits (UG), Introduction to Electronics (UG), Analog VLSI Circuits (PG), Semiconductor Device Modeling (PG) and VLSI Circuits and Systems (PG). Teaching feedback above four
  • Faculty Consultant for different private organizations working in the area of analog IC design 
  • Principal Investigator of three research projects sponsored by Indian Govt organizations.
  • Supervise Doctoral Thesis and Master level thesis (Successfully guided 5 Ph.D. and 47 M.Tech/M.S thesis)
  • Was Leading IC design activity in the Institution (through National Semiconductor foundry)
  • Took initiative to get MoU signed with SCL Laboratory, enhancing collaboration opportunity to get our design implemented.
  • Organized a Short-term course on “CMOS Analog Design” for Scientists of ISRO
  • Delivered an Invited talk on “An Overview of Input/Output Buffers” in a National Conference
  • Conducted on-site and on-line classes on “Analog circuits” through Talk to 10K teacher program at IIT Kharagpur
  • Nine prototype Test Chips have been designed, got fabricated and tested for silicon validation of innovative circuits
  • Overall citation of our 82 publications is 640 and the H-factor is 12.

Research Statement

The area of my research work is Analog CMOS VLSI Circuit/System Design. Activities in my research team can be broadly classified into two categories. The first one involves architecture development and prototype design of analog circuits/systems in three specific topics namely, Interface unit for high-speed data link, On-chip DC-DC converter and Signal acquisition front-end. The second category of our work is about developing and prototyping automatable design methodologies for frequently used analog circuits/systems.
For high-speed data link, we have proposed a number of power-efficient high-speed data receivers and transmitters with an active terminator. Some of our design also enables simultaneous two-way data transmission over a common link.
We have proposed a switching scheme for switched-capacitor based DC-DC converter which improves the power efficiency by 5-10%. We have proposed a scheme of dynamically adjusting switching frequency of switched-capacitor based DC-DC converter which helps to maintain high power efficiency across a wide range of load current. Both, the switching scheme and switching frequency adjustment are generic enough to be applied for buck and boost converters.

We have proposed a Geometric Programming (GP) based circuit sizing method for optimum design. The sizing method is very fast and robust. The GP based optimization method has been upgraded to address practical design considerations and issues in sub-micron technologies. Prototype codes have been implemented to design a number of practical circuits meeting competitive specifications. We also have proposed a design methodology for an analog system utilizing the GP-based circuit sizing method. A prototype code has been implemented to design Analog-to-Digital Converter (ADC). To design an ADC, normally, an experienced designer takes more than 3 months, which is performed by the prototype code in 6 hours.


  • 1 Design Automation Of CMOS Analog Circuits And Systems
  • 2 On-chip Power Management System
  • 3 Analog Interface Circuits For High Speed Data Link
  • 4 Analog Circuits For Signal Acquisition Front-end System


  • Mukherjee R., Basu J. , Mandal P. , Guha P. K., A review of micromachined thermal accelerometers, Journal of Micromechanics and Microengineering, 27, 2017
  • Wary N., Mandal P, Current-mode triline transceiver for coded differential signaling across on-chip global interconnects, IEEE Transaction of VLSI, 25, 2575-2587, 2017
  • Wary N., Mandal P., High-speed energy-efficient bi-directional transceiver for on-chip global interconnects, IET Circuits, Devices and Systems, 319-327, 2015
  • R. Mukherjee, P.K. Guha and P. Mandal, Sensitivity improvement using optimized heater design for dual axis thermal accelerometers, Microsystem Technologies, 2015
  • Sudip Kundu, and Pradip Mandal, ISGP: Iterative Sequential Geometric Programming for Precise and Robust Analog Circuit Sizing, Integration, the VLSI Journal, 47, 510-531, 2014
  • Samiran Dam and P. Mandal, Modeling and Design of CMOS Analog Circuits through Hierarchical Abstraction, Integration, the VLSI Journal, 449-462, 2013
  • Biswajit Maity, Soumya Gangula and P. Mandal, Design and Implementation of an Area and Power Efficient Switched-Capacitor Based Embedded DC-DC Converter, Journal of Low Power Electronics, 8, 207-222, 2012
  • Kaushik Bhattacharyya and P. Mandal, Improvement of Performance of Dynamically Reconfigurable Switched Capacitor Based Non-Overlap Rotational Time Interleaved Embedded DC-DC Converter, Journal of Low Power Electronics, 8, 223-234, 2012
  • Vijaya Sankara Rao P, Debashis Banerjee and P. Mandal, Active Terminated Current-Mode Pre-emphasis Transmitter for PCI Express Standard, International Journal of Electronics and Communication, 65, 2011
  • Mrigank Sharad, Vijaya Sankara Rao P. and P. Mandal, Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications, Analog Integrated Circuits and Signal Processing, 42, 361-377, 2011
  • Vijaya Sankara Rao P. and P. Mandal, Current-Mode Analog Interface for High-Speed Low-Current Differential Signaling, International Journal of Electronics, 1007-1020, 2010
  • Tamal Das and P. Mandal, Switched-Capacitor Based Buck Converter Design Using Current Limiter, Journal of Low Power Electronics American Scientific Publisher, 2009
  • Maity A., Raghavendra R. G., Mandal P, Design of a low power voltage regulator for high dynamic range of load current, International Journal of Electronics, 95, 743-757, 2007
  • P. Mandal and V. Visvanathan, CMOS Op-Amp Sizing Using a Geometric Programming Formulation, Transactions on Computer Aided Design of Integrated Circuits and Systems, 20, 22-38, 2001
  • P. Mandal and V. Visvanathan, Self Biasing of High Performance Folded Cascode CMOS Op-Amp by, International Journal of Electronics, 87, 795- 808, 2000
  • P. Mandal and V. Visvanathan, Active Biasing of Multi Stage CMOS Op-Amps, International Journal of Electronics T, 8, 933-946, 1999


  • Development and Demonstration of Integrated Instrumentation System for Quantitative Detection of Water Contaminants with Information Database for Surveillance of Waterborne Diseases, Client: Department of Science and Technology(DST), Co-P.I.: Pradip Mandal, Completed
  • Development and Demonstration of Integrated Instrumentation System for Quantitative Detection of Water Contaminants with Information Database for Surveillance of Waterborne Diseases, Client: Ministry of Electronics and Information Technology, Co-P.I.: Pradip Mandal, Completed


  • Best Paper Award at the IEEE 21st International Conference on VLSI Design - Year: 2008


  • Thermal Accelerometer with Improved Sensitivity : Submitted
  • Thermal Accelerometer with Active Temperature Sensor
  • An Integrated Signal acquisition cum Conditioning system

Research Group

Card image
Perumalla Subrahmanyam
Ph. D.
Research Scholars
Analog and Mixed-signal design